多功能全數位鎖相迴路

Abstract

一個具展頻電路、非整數除數電路、突波抑制電路以及高階濾波器的全數位鎖相迴路被提出。通過三角波形量變曲線產生器來調變輸出頻率所得到模擬結果顯示被抑制的電磁干擾為30分貝。參考突波可能會混合週遭通道訊號的問題可以利用突波抑制電路來處理。當通道間距小的情況，非整數除數電路可以被利用，因為它具有高頻率解析度。在輸入噪聲存在的情況下，全數位鎖相迴路能透過開啟無限脈衝響應濾波器來將整體迴路提升到更高階進而抑制輸入噪聲。除此之外，本篇論文將會針對寄生基調在使用高階全數位鎖相迴路時會更靠近主基調的現象做分析。 晶片設計利用TSMC 40nm GP 1P9M CMOS製程進行電路模擬與實現，除了數位控制振盪器及線性穩壓器之外，皆使用標準元件，因此設計可以很容易的轉換到其它製程。整體電路的核心面積為0.0257平方毫米。操作在輸出訊號為5376百萬赫茲的情況下，模擬所得到的週期抖動為百分之0.05單位間隔。操作在輸出訊號為5376百萬赫茲且輸入參考時脈訊號為84百萬赫茲時，整體功率消耗為5.36毫瓦特。

An ADPLL with spread spectrum circuit, fractional-N circuit, spur reduction circuit, and higher order loop filter is presented. By modulating the output frequency with the triangular profile generator, the simulated EMI reduction can be 30dB. The reference spurs which may mix the signals from adjacent channels can be dealt with by using the spur reduction circuit. When the channel spacing is small, the fractional-N circuit can be utilized for its higher frequency resolution. In the presence of input noise, the ADPLL can select the whole loop as a higher order by turning on the IIR filter to attenuate input noise. Moreover, the phenomenon that spurious tone is getting closer to main tone at higher-order ADPLL, will be analyzed in this thesis. The chip has been designed and implemented in TSMC 40nm GP 1P9M CMOS process technology. In the proposed ADPLL, all logic cells except the DCO and the LDO are using standard cell, therefore, it can be easily migrated from one technology to another. The total area of the ADPLL core is 0.0257mm2. The simulated RMS jitter from a 5.376GHz output frequency is 0.05% UI. The total power consumption is 5.36mW at 5.376GHz output frequency and 84MHz reference clock.