全數位鎖相迴路及其應用之研究

Abstract

全數位鎖相迴路的優點在於可以有效率的將設計轉移到不同的製程上，減少系統重新設計的時間。在本論文中，我們提出了全新的迴路演算法，以使系統更有效率且更為穩健。全數位鎖相迴路比起現有的設計，透過全數位化的計算及頻率蒐尋，不論在鎖定時間、鎖定範圍或系統的穩定度上都有較好的表現。本論文設計兩種數位頻率合成器和兩種時脈復原電路，以符合不同系統的規格。兩種數位頻率合成器分別是「基本型的數位頻率合成器」 和 「時間數位轉換器為基礎的數位頻率合成器」；而兩種時脈復原電路為「全數位鎖相迴路的時脈復原電路」和「混合結構的時脈復原電路」。 基本型的數位頻率合成器提供了高成本效益的內建時脈產生器，並可符合晶片內部的倍頻要求，其解析度可達到50ps。經由量測，在3.3伏特的工作電壓可以產生65MHz~165MHz的輸出頻率，且輸出抖動小於±50ps。在考量高雜訊的工作環境下，提昇系統的穩健度，而提出一個以數位時間轉換器為基礎的頻率合成器。並且為了增加數位頻率合成器在頻率上的解析度，而設計利用電晶體的基底效應，實現高解析度的全數位控制震盪器。經由量測的結果顯示，週期的抖動比例可以改進24dB以上，並且此數位頻率合成器的輸出頻率在3.0伏特的工作電壓，可從50MHz~185MHz，其解析度達250fs。 在NRZ時脈復原電路以全數位鎖相迴路為基礎的設計方面，可以在一個有效的資料變化內將時脈復原，並最快可達高速時脈的四分之一。鎖定範圍為( )，其中 是輸入訊號的週期。為了復原更高速率的NRZ訊號，而另外提出了一種混合式的架構。這個架構結合了數位頻率合成器和全數位鎖相迴路的技術，可以用來復原36~165Mbps的NRZ訊號，可鎖定範圍為( )，其代價為需要較多有效的資料變化才能鎖定。 依據上述全數位鎖相迴路的概念，本論文完成了兩種不同應用方面的設計；一個是340MHz~800MHz的時脈產生器，另一個是無線區域網路使用的直接序列展頻基頻處理器。為了達到更高的工作頻率，我們使用了反相器陣列震盪器來實現，在3.3伏特的工作電壓下，輸出頻率可從340MHz~800MHz，並經由實際量測，其頻率抖動小於64ps @800MHz。而在無線區域網路的應用方面，使用全數位的設計方法可以降低設計所需的代價、縮短設計時程並讓設計更有效率。利用所提出的全數位設計方式，製作完成了4/2/1Mbps直接序列展頻基頻處理器的晶片及其驗證。這顆處理器包含了以低功率可變長度指標存取記憶體為基礎的匹配濾波器、全數位時脈復原電路、使用反三角函數完成的DQPSK解調器和內建中央控制器。量測的結果顯示這顆晶片的功率消耗在2.5V/100MHz時小於65mW；而在5V/100MHz時則小於210mW。 值得強調的是所有提及的演算法及架構皆可利用硬體描述語言及合成軟體來完成，屬於可攜式的設計，並可以當做智慧財產IP來使用。而所有提及的設計方式也都製作成晶片（使用0.6um CMOS SPTM和0.35um CMOS DPTM兩種製程）並完成了實際的量測與驗證。由這些結果證實，本論文所提出的全數位鎖相迴路非常適用於單晶片系統的整合設計，尤其是在數位通訊的應用領域上。

All digital phase-locked loop (ADPLL) has a good capacity of portable issues to reduce system-turnaround time during process migration. In order to make system more efficient and robust, new algorithms for ADPLL have been developed in this thesis. By period estimation of phase error and 2-stage frequency search, the proposed ADPLL solution can achieve better performance, compared to available PLL’s solutions, in terms of lock-in time, pull-in range, and system stability. Two digital frequency synthesizer (DFS), and two clock recovery circuits are explored to meet different system specifications, namely basic DFS and time-to-digital (TDC) based DFS, ADPLL based clock recovery and mixed structure based clock recovery. The basic DFS is a cost-efficient design for on-chip clock generator, which can provide any number of frequencies with 50ps output resolution. From tests, it can operate from 65 to 165MHz less than jitter at 3.3V. In order to make system-level integration more efficient in noisy environment, a new DFS based on TDC technique and mean process is proposed to improve system stability. For increasing frequency accuracy, a higher-resolution DCO is constructed by characteristic of transistor ─ body effect. As a result, the ratio of jitter per period can be improved more than 24dB and DCO output range can be from 50 to 185MHz under 250fs resolution. ADPLL based design can recover NRZ clock within one data transition and has maximum “f/4” recovering capability with locking range of T/2~3T/2, where tinput is T input period. To operate at higher data rate, a mixed structure is proposed to combine with DFS and ADPLL. This clock recovery can use to recover 36~165Mbps NRZ signal with locking range, however it needs several valid transitions to lock signals. Based on the proposed ADPLL concepts, two applications have been realized; one is 340~800MHz clock generator, and the other is DSSS baseband processor for wireless local area network (LAN). In order to achieve higher output frequency, a matrix-like DCO with parallel inverter bank is performed to make frequency range from 340 to 800 MHz with <64ps jitter at 3.3V. For DSSS baseband processor, all digital methodology can reduce design effort to make turnaround time more efficient. Based on the proposed methodology, a 4/2/1Mbps DSSS baseband processor with low-power variable-length Pointer Access Memory (PAM) based matched filter, all digital clock recovery, DQPSK demodulator, and on-chip central controller, has been designed and verified on silicon. Test results show that this DSSS baseband transceiver chip has power consumption of (<65mW @ 2.5V/100MHz)/(210mW @ 5V/100MHz). Note that all above-mentioned approaches belong to portable and intellectual property (IP) based designs that can be developed by hardware description language (HDL) and synthesized for a target cell library. Each of them has been verified on silicon using an in-house 0.6um CMOS Single Poly Triple Metal (SPTM) cell library and 0.35um CMOS Double Poly Triple Metal (DPTM) cell library. As a result, the proposed ADPLL approaches are well-suited for system-level integration, especially in those digital communication application domains 1-1 Thesis Motivation 1 1-2 Thesis Outline 5 2. Principles of All Digital Phase-Locked Loop 10 2-1 Basic Concept of PLLs 11 2-2 Algorithm Description 12 2-3 The Proposed Architecture 16 2-4 Simulation Results and Discussion 18 2-5 Summary 20 3. Digital Frequency Synthesizer 22 3-1 Basic Concept 23 3-1-1 Frequency-Search Algorithm 24 3-1-2 The Proposed Architecture 27 3-1-3 Measured Results 32 3-2 HDL Jitter Model 37 3-3 Jitter Reduction 39 3-4 TDC based Structure 40 3-4-1 Algorithm Description 40 3-4-2 The Proposed Architecture 43 3-4-3 Circuit Designs 46 3-4-4 Measured Results 53 3-5 Discussion and Summary 57 4. All Digital Clock Recovery 59 4-1 ADPLL based Structure 60 4-1-1 Algorithm Description 60 4-1-2 The Proposed Architecture 64 4-1-3 Measured Results 67 4-2 Mixed Structure 70 4-2-1 Operating Description 71 4-2-2 The Proposed Architecture 73 4-2-3 Simulation Results 79 4-3 Discussion and Summary 82 5. Applications ─ (I): 340~800 MHz Clock Generator 83 5-1 The Proposed Algorithm 83 5-1-1 Frequency Search 84 5-1-2 Pull-in Algorithm 85 5-1-3 Propagation-Delay Issue 87 5-2 The Proposed Architecture 87 5-2-1 Double Ring Oscillator Structure 87 5-2-2 Single Ring Oscillator Structure 90 5-2-3 Band Allocation 91 5-3 Digital Controlled Ring Oscillator 92 5-4 Measured Results 94 5-5 Discussion and Summary 100 6. Applications ─ (II): DSSS Baseband Processor 101 6-1 Chip Description 125 6-1-1 Synchronization 126 6-1-2 Quantization Level 128 6-1-3 DQPSK Demodulation 129 6-2 Chip Architecture 129 6-2-1 Offset Estimation 130 6-2-2 Complex Measurement 131 6-2-3 False-Alarm Consideration 132 6-2-4 I/O Management 132 6-3 Circuit Designs 132 6-3-1 Variable-Length PAM based Matched Filter 132 6-3-2 DQPSK Demodulator 136 6-3-3 On-Chip Central Controller 138 6-4 Implementation and Measured Results 141 6-5 Discussion and Summary 123 7. Conclusion and Future Works 145 References 124 Appendix A: System Capacity 130 A-1 System Model 104 A-2 Mathematic Derivation of Reverse Links 106 A-3 Mathematic Derivation of Forward Links 112 A-4 Simulation Results 120