工作於1 kHz至10 MHz並具有良好抗雜訊能力的一位元量化全數位式鎖相迴路

Abstract

在本論文中，我們嘗試設計一個應用於1 kHz至10 MHz的通用型一位元量化全數位式鎖相迴路。本電路主要應用於馬達、電力輸出設備以及其他工作於該頻段的電路或系統。由於超寬頻的鎖相迴路實現上很困難，因此我們提出一種方法能夠有效鎖定未知頻率的信號。同時，我們希望本電路能適應各種工作環境，因此所提出的架構具有良好的抗雜訊能力。 在所提的架構中，我們將鎖定程序分為兩個部份：捕獲程序與追蹤程序。捕獲程序利用二分法來搜尋可能的頻率範圍；追蹤程序負責修正微小的頻率差異並補償相位誤差。由模擬結果顯示，本架構在SNR=0 dB的環境下都能具有良好的表現，成功完成一個同時具備超寬捕獲範圍及良好抗雜訊能力的全數位式鎖相迴路。

In this thesis, we would like to design a universal one-bit all digital phase-locked loop (ADPLL) which can be applied in the frequency range from 1 kHz to 10 MHz. The applications of this circuit include motor control, power supply design and other applications that work in the specified frequency range. We propose an efficient and reliable scheme to lock the unknown input signal within the ultra-wide frequency region. Moreover, the proposed scheme has strong noise immunity, which can work well in serious noisy environment. We divide the locking process into two parts: Acquisition Process and Tracking Process. We use the binary search to search the possible region of the input frequency in the acquisition process. We further use the tracking process to remove the frequency difference and compensate the phase error. According to our simulation results, the proposed scheme has superior performance for the designed frequency range even when SNR = 0 dB.