使用自我校正時間放大器與相位內插數位控制振盪器且具有1ps解析度時間數位轉換器之快速鎖定全數位鎖相迴路

Abstract

近年來鎖相迴路廣泛的使用在SOC (System On Chip)應用上，例如時脈資料回復電路、無線通訊系統收發器等。早期鎖相迴路發展中，以類比鎖相迴路為主，然而隨著製成尺寸不斷的縮小與改變，類比電路也必須重新設計。除此之外，類比電路中使用到被動元件耗費較多的面積，比起數位電路速度也較慢。在近年中，全數位鎖相迴路普遍使用在鎖相迴路系統當中。 在本篇論文中，以全客戶式設計完成全數位式鎖相迴路，第一顆晶片提出多級時間數位轉換電路的創新，利用不同的時間數位轉換電路交互使用，中間插入高倍數的時間放大器，產生出解析度為1ps的多級時間數位轉換器。對於時間數位轉換器中的時間放大器使用自我校正機制，以達到更準確的放大倍率。第一顆晶片中採用週期線性的數位控制振盪器，振盪頻率範圍為140MHz~1220MHz。第二顆晶片以第一顆晶片作為電路基礎，加入快速鎖定機制以及使用相位內插數位控制振盪器。相位內插數位控制振盪器振盪頻率範圍為150MHz~1450MHz。 兩個所提出的晶片皆將頻率鎖定至800MHz；第一顆晶片的量測結果，時脈抖動為21.67ps的峰對峰值時間抖動(Peak to Peak jitter)，功率消耗為21.32mW，核心面積為0.1845mm¬2。而第二顆晶片的模擬平均峰對峰值時間抖動(Peak to Peak Jitter)為21.9ps，功率消耗為18.2mW。

Phase-locked loops (PLLs) are widely used for SOC applications, such as Clock and Data Recovery (CDR) and wireless communication systems. In the early development of PLL, PLL design was realized by analog approach. However, with the process technology scaling down, analog circuits need to be redesigned. In additional, analog PLL circuits use passive components, which occupy lots of area, and the speed of analog PLL circuits is usually slower than that of digital PLL circuits. ADPLLs have becomes popular in recent years. In this thesis, we implement the ADPLL by using full-custom design flow. In the first chip, we propose an innovative multi-stage TDC and a Time Amplifier to achieve 1ps resolution. The Time Amplifier with calibration circuit generates precise amplification. The proposed DCO with a linearly periodic digital-to-frequency relationship operates 140MHz to 1220MHz. In the second chip based on the first chip, a Frequency Tracking Engine (FTE) and Interpolation DCO are introduced to reduce the locking time and increase the resolution of DCO, and the operation range is from 150MHz to 1450MHz. Both of chips we designed to locked at 800MHz. The measurement results show that the first chip has a peak-to-peak jitter of 21.67ps. The ADPLL has an area of 0.1845mm2, and the power dissipation of 21.32mW. For the second chip, there are post-simulation value of 21.9ps peak-to-peak jitter and the power dissipation of the ADPLL is 18.2mW.