Accelerating Functional Timing Analysis with Encoding Duplication Removal and Redundant State Propagation

Abstract

Functional timing analysis (FTA) emerges for better timing closure than static timing analysis (STA) by providing the true delay of the circuit as well as its input pattern. For Satisliability(SAT)-based VIA, a search problem for circuit delay can be expressed by clauses corresponding to circuit consistency function (CCF) and timed characteristic function (TCF). In particular, the clause number tends to grow exponentially as the circuit size increases, lengthening runtime for FTA. However, when formulating TCT, numerous clauses and literals are found useless. Therefore, two key techniques are proposed: (1) Encoding Duplication Removal (EDR) for removing those literals that are previously encoded in CCF but now duplicated in TCF, and (2) Redundant State Propagation (RSP) for propagating redundant states of nodes to help prune TCF clauses. Experiments indicate that under the worst-case delay of each benchmark circuit, EDR and RSP successfully reduce averagely 49% of clauses, 65% of literals, and 52% runtime on seven benchmark circuits for FTA.