標題: A Hardwired Priority-Queue Scheduler for a Four-Core Java SoC
作者: Tsai, Chun-Jen
Lin, Yan-Hung
資訊工程學系
Department of Computer Science
關鍵字: multi-core processor;multi-level priority-queue scheduler;SoC;embedded computing;hardwired OS kernel
公開日期: 1-一月-2018
摘要: This paper presents the design and implementation of a hardwired thread scheduler circuit with multi-level priority queues for a four-core Java application processor. A hardwired thread scheduler is much more efficient than the software thread scheduler in a software OS kernel, such as Linux. Since the hardware scheduler can operate in parallel with the processor cores, complex scheduling decisions can be made while the processor cores are running applications. In addition, single-cycle context-switching is possible and no processor core has to waste time running the scheduler. Full-system implementation of a four-core Java processor with the hardware scheduler has been verified using a Xiliox Kintex-7 FPGA device. Performance evaluations show that the proposed system scales up very well and is promising for deeply-embedded multi-thread applications such as the automatic driver assistance systems or the drones.
URI: http://hdl.handle.net/11536/150862
ISSN: 0271-4302
期刊: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
顯示於類別:會議論文