標題: | Circuit-Simulation-Based Multi-objective Evolutionary Algorithm with Multi-Level Clock Driving Technique for a-Si:H TFTs Gate Driver Circuit Design Optimization |
作者: | Hung, Sheng-Chin Chen, Chieh-Yang Chiang, Chien-Hsueh Li, Yiming 分子醫學與生物工程研究所 電機工程學系 電信工程研究所 Institute of Molecular Medicine and Bioengineering Department of Electrical and Computer Engineering Institute of Communications Engineering |
關鍵字: | a-Si:H TFTs;amorphous silicon gate driver circuits;display panel design optimization;multiobjective evolutionary algorithm;unified optimization framework |
公開日期: | 1-一月-2015 |
摘要: | In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 mu s and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique. |
URI: | http://dx.doi.org/10.3233/978-1-61499-484-8-157 http://hdl.handle.net/11536/150897 |
ISSN: | 0922-6389 |
DOI: | 10.3233/978-1-61499-484-8-157 |
期刊: | INTELLIGENT SYSTEMS AND APPLICATIONS (ICS 2014) |
Volume: | 274 |
起始頁: | 157 |
結束頁: | 166 |
顯示於類別: | 會議論文 |