Investigation on Latch-Up Path between I/O PMOS and Core PMOS in a 0.18-mu m CMOS Process

Abstract

This work studied the latch-up path between two PMOS devices powered by different supply voltages in a 0.18- m CMOS process. In IC field applications, such a non-typical latch up path between two PMOS devices was ever fired to cause unrecoverable failures. Through the silicon test chip, the latch-up path between I/O PMOS and core PMOS was investigated in details. The measurement results from the silicon chip with split test structures can be used to investigate the design rules on anode-to-cathode spacing and guard ring placement to prevent such PMOS-to-PMOS latch-up issue. In chip layout of IC products, the PMOS devices in different power domains shall be carefully checked to prevent the occurrence of such unexpected latch-up path.