A Novel Double-gated Nanowire TFT and Investigation of Its Size Dependency

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DC Field	Value	Language
dc.contributor.author	Chen, Wei-Chen	en_US
dc.contributor.author	Lin, Chuan-Ding	en_US
dc.contributor.author	Lin, Horng-Chih	en_US
dc.contributor.author	Huang, Tiao-Yuan	en_US
dc.date.accessioned	2014-12-08T15:24:26Z	-
dc.date.available	2014-12-08T15:24:26Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-1-4244-2784-0	en_US
dc.identifier.uri	http://hdl.handle.net/11536/16954	-
dc.description.abstract	A simple method for fabricating poly-Si nanowire (NW) TFT with multiple gates is proposed and characterized. In this structure, NW is formed mainly using both anisotropic and highly selective isotropic plasma etching. It is found that when the size of NW is scaled down, double-gated operation provides more improvement. Furthermore, by utilizing this unique independent double-gated Configuration, the function of threshold voltage modulation is investigated.	en_US
dc.language.iso	en_US	en_US
dc.title	A Novel Double-gated Nanowire TFT and Investigation of Its Size Dependency	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF TECHNICAL PROGRAM: 2009 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS	en_US
dc.citation.spage	121	en_US
dc.citation.epage	122	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000272451000054	-
Appears in Collections:	Conferences Paper