2-l.evel FIFO architecture design for switch fabrics in network-on-chip

Abstract

The network-on-chip (NoC) architecture provides the integrated solution for system-on-chip (SoC) design. The buffer architecture and sizes, however, dominate the performance of NoC and influence on the design of arbiters in the switch fabrics. The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures without increasing the buffer sizes. The concept of the shared memory mechanism and multiple accesses for the buffers are developed. The FIFO architecture is implemented and simulated with TSMC 0.13um CMOS technology by HSPICE and Verilog. The operation frequency of the 2-level FIFO reaches 400MHz.