標題: | Novel FFT Processor with Parallel-In-Parallel-Out in Normal Order |
作者: | Hu, Hsiang-Sheng Chen, Hsiao-Yun Jou, Shyh-Jye 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2009 |
摘要: | A novel FFT processor that can provide parallel-in-parallel-out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16c. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm(2) by using 90 rim, IV CMOS process. |
URI: | http://hdl.handle.net/11536/18089 |
ISBN: | 978-1-4244-2781-9 |
期刊: | 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM |
起始頁: | 150 |
結束頁: | 153 |
顯示於類別: | 會議論文 |