The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications

Abstract

This work presents a new technique to implement an active polyphase filter. In this design, the currents mirrored from capacitors and transistors realize the high-pass and low-pass signals, respectively The multi-stage structure, which is commonly used in RC networks, expands the frequency bandwidth. Furthermore, a constant-gin bias circuit is used to decrease the sensitivities of gain and bandwidth to temperature and process variations. HSPICE is simulated to confirm the performances. The voltage gain is 8.1dB and THD is -48dB when a +20MHz, 100mV quadrature signal is applied. The image-rejection ratio exceeds 60dB over the frequency range of -15.4MHz similar to - 44.6MHz. The polyphase filter is implemented with 0.18mum CMOS technology and the power dissipation is 6.85mW with a 1.8V power supply. Simulations of various corners and temperatures show that the variations in gain and frequency are effectively controlled.