標題: VLSI design of a priority arbitrator for shared buffer ATM switches
作者: Lin, YS
Yang, SC
Fang, SJ
Shung, CB
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1997
摘要: Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority control selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA): and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8x8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130k gates in a chip area of 137.88 mm(2) using 0.6 mu m CMOS technology.
URI: http://hdl.handle.net/11536/19724
ISBN: 0-7803-3583-X
期刊: ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE
起始頁: 2785
結束頁: 2788
顯示於類別:會議論文