A cost-effective VLSI architecture for high-throughput sequential decoder

標題:	A cost-effective VLSI architecture for high-throughput sequential decoder
作者:	Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	1996
URI:	http://hdl.handle.net/11536/19806
ISBN:	0-7803-3073-0
期刊:	ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4
起始頁:	328
結束頁:	331
Appears in Collections:	Conferences Paper