| 標題: | Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's |
| 作者: | Ker, MD Wu, CY Cheng, T Chang, HH Wu, MJN Yu, TL 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 1995 |
| URI: | http://hdl.handle.net/11536/19997 |
| ISBN: | 7-5053-3285-6 |
| 期刊: | PROCEEDINGS OF THE FOURTH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY |
| 起始頁: | A193 |
| 結束頁: | A195 |
| Appears in Collections: | Conferences Paper |
- 互補式金氧半積體電路中輸入及輸出緩衝級之新型佈局設計 / 黃建章;Huang, Chien-Chang;吳重雨, 柯明道;Chung-Yu Wu, Ming-Dou Ker
- Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area / Ker, MD;Wu, CY;Huang, CC;Chen, TY
- New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness / Ker, MD;Chen, TY;Chang, HH
- 互補式金氧半積體電路之靜電放電保護電路及低同步切換雜訊輸出驅動級之設計 / 張恆祥;Chang Hun-Hsien;吳錦川;柯明道;Jiin-Chuan Wu
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