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dc.contributor.authorHan, Ming-Hungen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.contributor.authorChen, Hung-Binen_US
dc.contributor.authorCheng, Ya-Chien_US
dc.contributor.authorWu, Yung-Chunen_US
dc.date.accessioned2014-12-08T15:30:35Z-
dc.date.available2014-12-08T15:30:35Z-
dc.date.issued2013-06-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2013.2256137en_US
dc.identifier.urihttp://hdl.handle.net/11536/21856-
dc.description.abstractThe design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V-th) roll-off characteristics at supply voltage (V-DD) 1 V. Analyses of electron density and electric field distributions in ON-state and OFF-state also show that the JL devices have better ON-OFF current ratios. Regarding design aspects, the effects of channel doping concentration (N-ch) and Fin height (H)/width (W) on device V-th are also compared. In addition, the V-th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N-sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t(HL)) and low-to-high delay time (t(LH)) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.en_US
dc.language.isoen_USen_US
dc.subject3-D simulationen_US
dc.subjectFinFETen_US
dc.subjectinverter circuiten_US
dc.subjectjunctionlessen_US
dc.subjectshort channelen_US
dc.subjectstatic random access memory (SRAM)en_US
dc.titleDevice and Circuit Performance Estimation of Junctionless Bulk FinFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2013.2256137en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume60en_US
dc.citation.issue6en_US
dc.citation.spage1807en_US
dc.citation.epage1813en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000319355500002-
dc.citation.woscount3-
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