Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Ming-Hung | en_US |
dc.contributor.author | Chang, Chun-Yen | en_US |
dc.contributor.author | Chen, Hung-Bin | en_US |
dc.contributor.author | Cheng, Ya-Chi | en_US |
dc.contributor.author | Wu, Yung-Chun | en_US |
dc.date.accessioned | 2014-12-08T15:30:35Z | - |
dc.date.available | 2014-12-08T15:30:35Z | - |
dc.date.issued | 2013-06-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2013.2256137 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/21856 | - |
dc.description.abstract | The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V-th) roll-off characteristics at supply voltage (V-DD) 1 V. Analyses of electron density and electric field distributions in ON-state and OFF-state also show that the JL devices have better ON-OFF current ratios. Regarding design aspects, the effects of channel doping concentration (N-ch) and Fin height (H)/width (W) on device V-th are also compared. In addition, the V-th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N-sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t(HL)) and low-to-high delay time (t(LH)) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 3-D simulation | en_US |
dc.subject | FinFET | en_US |
dc.subject | inverter circuit | en_US |
dc.subject | junctionless | en_US |
dc.subject | short channel | en_US |
dc.subject | static random access memory (SRAM) | en_US |
dc.title | Device and Circuit Performance Estimation of Junctionless Bulk FinFETs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2013.2256137 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 60 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 1807 | en_US |
dc.citation.epage | 1813 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000319355500002 | - |
dc.citation.woscount | 3 | - |
Appears in Collections: | Articles |
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