標題: Performance Comparison Between Bulk and SOI Junctionless Transistors
作者: Han, Ming-Hung
Chang, Chun-Yen
Chen, Hung-Bin
Wu, Jia-Jiun
Cheng, Ya-Chi
Wu, Yung-Chun
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Fin-shaped field-effect transistor (FinFET);junctionless (JL);3-D simulation
公開日期: 1-二月-2013
摘要: The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable ON/OFF current ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an ON/OFF current ratio of 10(5) at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage V-th of the JL bulk FinFET can be easily tuned by varying substrate doping concentration N-sub. The modulation range of V-th as N-sub changes from 10(18) to 10(19) cm(-3), which is around 30%.
URI: http://dx.doi.org/10.1109/LED.2012.2231395
http://hdl.handle.net/11536/21020
ISSN: 0741-3106
DOI: 10.1109/LED.2012.2231395
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 34
Issue: 2
起始頁: 169
結束頁: 171
顯示於類別:期刊論文


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