標題: | Minimizing Clock Latency Range in Robust Clock Tree Synthesis |
作者: | Liu, Wen-Hao Li, Yih-Lang Chen, Hui-Chi 資訊工程學系 Department of Computer Science |
公開日期: | 2010 |
摘要: | Given the extensive study of clock skew minimization, in the ISPD 2009 Clock Network Synthesis (CNS) Contest, clock latency range (CLR) was initially minimized across multiple supply voltages under capacitance and slew constraints. CLR approximates the summation of the clock skew and the maximum source-to-sink delay variation for multiple supply voltages. This work develops an efficient three-stage clock tree synthesis flow for CLR minimization. Firstly, a balanced clock tree with small skew is generated. Secondly, buffer insertion and wire sizing minimizes delay variation without violating the slew constraint. Finally, skew is minimized by inserting snaking wires. Experimental results reveal that the proposed flow can complete all ISPD'09 benchmark circuits and yield less CLR than the top three winners of ISPD'09 CNS contest by 59%, 52.7% and 35.4% respectively. Besides, the proposed flow can also run 5.52, 1.86, and 7.54 times faster than the top three winners of ISPD'09 CNS contest respectively. |
URI: | http://hdl.handle.net/11536/25454 |
ISBN: | 978-1-4244-5765-6 |
期刊: | 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010) |
起始頁: | 384 |
結束頁: | 389 |
顯示於類別: | 會議論文 |