Efficient Inter-layer Prediction Hardware Design with Extended Spatial Scalability for H.264/AVC Scalable Extension

Abstract

To support inter-layer prediction with arbitrary frame resolution ratio between successive spatial layers, the scalable video coding (SVC) adopts the mechanism of extended spatial scalability (ESS) to achieve it but with noticeable hardware implementation complexity due to the numerous multiplication operations. Therefore, this paper proposes a hardware efficient inter-layer prediction architecture design with ESS by means of accumulator approach. In addition, an area efficient inter-layer interpolator architecture and simplified transform block identification scheme are also proposed to further reduce hardware costs. Simulation results demonstrate that our proposed architecture can significantly save gate count when compared to direct implementation approach.