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dc.contributor.authorJiang, JHen_US
dc.contributor.authorJou, JYen_US
dc.contributor.authorHuang, JDen_US
dc.date.accessioned2014-12-08T15:44:00Z-
dc.date.available2014-12-08T15:44:00Z-
dc.date.issued2001-04-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/92.924031en_US
dc.identifier.urihttp://hdl.handle.net/11536/29741-
dc.description.abstractFunctional decomposition has recently been adopted for look-up tabel (LUT)-based field-programmable gate array (FPGA) technology mapping with good results. In this paper we propose a novel method to unify functional single;output and multiple-output decomposition. We first address a compatible class encoding algorithm to minimize the number of compatible classes in the image function. After applying the encoding algorithm, we can therefore improve the decomposability in the subsequent decomposition of the; image function. The above encoding algorithm is then extended to encode multiple-output functions through the construction of a hyperfunction, Common subexpressions among these multiple-output functions can be extracted during the decomposition of the hyperfunction, Consequently, we can handle multiple-output decomposition in the same manner as single-output decomposition. Experimental results show that our algorithms are promising.en_US
dc.language.isoen_USen_US
dc.subjectcompatible class encodingen_US
dc.subjectFPGAen_US
dc.subjectfunctional decompositionen_US
dc.subjecttechnology mappingen_US
dc.titleUnified functional decomposition via encoding for FPGA technology mappingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/92.924031en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume9en_US
dc.citation.issue2en_US
dc.citation.spage251en_US
dc.citation.epage260en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000169035300002-
dc.citation.woscount3-
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