| 標題: | Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping |
| 作者: | SHEN, WZ HUANG, JD CHAO, SM 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 1995 |
| URI: | http://hdl.handle.net/11536/20051 |
| ISBN: | 0-89791-653-0 |
| ISSN: | 0738-100X |
| 期刊: | 32ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1995 |
| 起始頁: | 65 |
| 結束頁: | 69 |
| Appears in Collections: | Conferences Paper |
- BDD based lambda set selection in Roth-Karp decomposition for LUT architecture / Jiang, JH;Jou, JY;Huang, JD;Wei, JS
- A variable partitioning algorithm of BDD for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD;Wei, JS
- ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping / Huang, JD;Jou, JY;Shen, WZ
- 用戶可規劃閘陣列之邏輯合成與分割 / 黃俊達;Huang, Juinn-Dar;沈文仁, 周景揚;Wen-Zen Shen, Jing-Yang Jou
- Unified functional decomposition via encoding for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD
- LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS / HWANG, TT;OWENS, RM;IRWIN, MJ;WANG, KH
- Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture / Huang, JD;Joy, JY;Shen, WZ
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