標題: BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
作者: Jiang, JH
Jou, JY
Huang, JD
Wei, JS
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1996
摘要: Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than those of the previous approach [1].
URI: http://hdl.handle.net/11536/19922
ISBN: 0-7803-3662-3
期刊: PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997
起始頁: 259
結束頁: 264
顯示於類別:會議論文