Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 王信華 | en_US |
dc.contributor.author | Sin-Hwa Wang | en_US |
dc.contributor.author | 李崇仁 | en_US |
dc.contributor.author | Chung-Len Lee | en_US |
dc.date.accessioned | 2014-12-12T02:12:04Z | - |
dc.date.available | 2014-12-12T02:12:04Z | - |
dc.date.issued | 1993 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT820430002 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/57996 | - |
dc.description.abstract | 本篇論文中,針對序向電路我們提出兩種方法來平行處理測試圖樣的產生, 第一種是使用多重啟發搜尋(multiple heuristics search)的方式,第二 種方法是對障礙做切割平行處理。。根據以上所提的兩種方法,我們再以 網路連接的 SUN Classic工作站上用C語言寫成程式經過實驗結果顯示,分 散式處理可以得到較佳的效率。 In this thesis we presented two distributed test generation system for sequential circuits. One uses a simulation-based test generator to be the central generator. And a multiple heuristics search method is proposed which may generate more effective pattern. The other uses a line-justification test generator, and a fault parallelism techniaue is used which can speed up the test generation. Two distributed test generation systems were implemented in the C language to run on a loosely-coupled network environment. The experimental results show that higher performance can be achieved than for a single machine. | zh_TW |
dc.language.iso | en_US | en_US |
dc.subject | 測試圖樣產生器;多重啟發搜尋;障礙切割平行; | zh_TW |
dc.subject | test generation;multiple heuristic search;fault parallelism simulation-based; | en_US |
dc.title | 分散式處理的序向電路測試圖樣產生器 | zh_TW |
dc.title | The Distributed Test Generation for Sequential Circuits | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
Appears in Collections: | Thesis |