同步序向電路之測試與可測性增強之研究

Abstract

本論文旨在研發新策略, 以改進序向電路之測試圖樣產生與可測試設計等 方法的效率. 在序向電路之測試圖樣產生過程中, 由於電路含有不可測及 難測的障礙, 使得測試圖樣產生器效率大減. 對於不可測障礙, 亟需良策 以先判定出這些障礙, 避免測試圖樣產生器虛耗時間尋找實際上不存在的 樣本. 吾人提出一簡單但有效的方法以判定這些不可測障礙, 其利用序向 電路之未定起始狀態, 傳遞此特性於整個電路, 以找出不可控制的線路及 正反器,再由一些所提出之規則, 判定四種所定義之不可測障礙, 其結果 顯示此方法可以比其他方法在短時間內找到更多的不可測障礙. 另一方 面, 針對難測的障礙, 吾人亦提出方法以解決之. 由於測試圖樣產生器會 花時間在判定不存在之正反器狀態, 而這些不存在狀態是不論用何樣本輸 入, 電路都無法到達的狀態. 如果不先找出這些不存在狀態, 測試圖樣產 生器在做判定時會耗費很多時間, 而進入無窮迴路或放棄的結果. 為此吾 人提出三個方法, 以找出序向電路的不存在狀態. 第一個方法是由未定起 始狀態出發, 瀏覽所有的存在狀態,如此即可得到完整的不存在狀態集合. 第二個方法也是尋找完整的不存在狀態集合, 但方法是為每個狀態尋找其 之可到達狀態集合, 再由這些資訊整理出結果. 第三個方法則只尋找出那 些能加快判定工作所需的不存在狀態, 其是根據由電路結構所繪出之正反 器關係圖,定出各個部份電路並加以模擬, 以得到測試圖樣產生過程中所 需之不存在狀態. 實驗證明這些方法可在短時間內找到所要之不存在狀 態, 而所得之不存在狀態在應用至測試圖樣產生過程後, 亦發現其能有效 地縮短測試圖樣產生過程所需的時間, 提高障礙涵蓋率及測試效率, 特別 是針對大電路及難找測試樣本的電路. 這些不存在狀態, 亦能用來輔助可 測試電路的設計, 根據一初步的測試圖樣產生器, 吾人收集欲驅動障礙所 需之正反器狀態, 以及可以傳遞至每個正反器的障礙數, 加以分析及量 化, 配合這些所需狀態包含不存在狀態的情形, 定出正反器於部份重置與 部份掃瞄時的選擇優先順序, 實驗結果顯示, 吾人可以選擇較少的正反器 以達成較易測之電路. This dissertation studies the strategies for improving the testing efficiency and the testability for synchronous sequential circuits. In sequential circuits, some faults are hard or impossible to begenerated tests, which degrades the efficiency of a test generator very much. For the untestable faults, it is worthwhile to identify them beforehand in order not to vainly search test patterns. A simpleyet efficient method is proposed to identify four types of untestablefaults in sequential circuits. The method makes use of the unknown initial state of flip-flops and propagates the characteristics throughout the circuit to find the uncontrollable lines and flip-flops. The untestable faults are classified into four types and are identified from the simulated results by rules. Comparing the results to other methods, it is obvious that our method can identify more untestable faults in short time. In addition to untestable faults, test generators including justification process have another problem that they may justify the flip-flops into invalid states. These states cannot be reached from the initial state of the circuit under whatever the input sequences. If not knowing or learning these invalid states information before or during test generation, the test generator may cost a lot of time for justification and the process may go into an infinite loop or abort at last. To prevent entering such a predicament, three algorithms are proposed to search the invalid states of a sequential circuit. The first algorithm explores all the valid states from an unknown initial state to search the complete set of invalid states. The second algorithm finds the complete set of invalid states by searching the reachable states for each state. The third algorithm searches the invalid states that need to be known for test generation to help stop justification early by analyzing dependency among flip-flops to simulate each partial circuit. Experimental results show that the algorithms can identify invalid states in short time. The obtained invalid states were also used in test generation to show that they can improve test generation significantly in the test generation time, the fault coverage and the detection efficiency, especially for larger circuits and those that were difficult to be generated tests. The information about invalid states can also be used to aid testable design. A method is proposed to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. From an initial test generation, information on required states for activating faults and the number of faults which can be propagated to flip-flops are obtained. These are analyzed and quantified, in which the required states covered by invalid states are also considered, to obtain the selection weights of flip-flops for reset or scan. Experiments show that this method can select less number of flip-flops for partial reset and scan while produce more testable circuits for benchmark circuits.