基於測試圖樣產生之序向電路的部分掃描設計

Abstract

部分掃描設計之理論業已受到大家公認，能夠經濟又有效率地改進序向電 路的可測試性。本篇論文研製一套以正反器內值為導向的部分掃描方法。 主要的追求目標是從產生測試圖樣的過程中，便能簡單利用正反器內值的 變化情形來汲取有用的相關資訊，並加以整合來作為我們選擇掃描正反器 之策略依據。是以，在我們的設計裡可以避開大量複雜的計算而省下可觀 的花費。同時由實驗數據顯示在與ETD之結果比較時，對大部分的 benchmark電路而言，本方法皆能以較少之測試圖樣同時掃描較少之正反 器而得較高之故障涵蓋率。 The partial scan design methodology has been recognized as a cost-efficient technique to improve the testability of sequential circuits. In this thesis, a flip-flop's value oriented partial scan approach is proposed. The main idea pursued here is to derive a flip-flop selection strategy just from the useful and easily accessed information in the test generation (TG) process. Parameters of UC, SR, TC, and RF are created and updated based on the value of flip-flop. In the end of TG, they are integrated to guide the decision making on flip- flop selection priority. Neither enormous arithmetic computation nor complicated processing is needed in our approach. Also experimental results show that higher fault coverage can be achieved by selecting less flip-flops and inputing less test patterns than those in ETD for most benchmaek circuits.