標題: | Power-oriented partial-scan design approach |
作者: | Jou, JY Nien, MC 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | design;VLSI;algorithms;partial scan approach;automatic test pattern generation |
公開日期: | 1-八月-1998 |
摘要: | Power consumption and testability are two of major considerations in modern VLSI design. A full-scan method had been used widely in the past, to improve the testability of sequential circuits. Owing to the lower overheads incurred, the partial-scan design has gradually become popular. The authors propose a partial-scan selection strategy which is based on the structural analysis approach and considers the area and power overheads simultaneously. A powerful sample-and-search algorithm is used to find the solution that minimises the user-specified cost function in terms of power and area overheads. The experimental results show that the sample-and-search algorithm derived by the authors can effectively find the best solution of the specified cost function, for almost all circuits, and, on average, the saving of overheads for each specific cost function is significant. |
URI: | http://hdl.handle.net/11536/32480 |
ISSN: | 1350-2409 |
期刊: | IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
Volume: | 145 |
Issue: | 4 |
起始頁: | 229 |
結束頁: | 235 |
顯示於類別: | 期刊論文 |