系統晶片/系統封裝之低測試成本方法研究

Abstract

在現代的系統晶片設計中，隨著系統設計越趨複雜，晶片測試成本占晶片製造成本比例越來越高，透過有效的測試策略來降低測試成本變成很重要的議題。在晶片測試的過程中，往往因為過高的功率消耗導致晶片燒燬、良率下降，因此我們針對測試功率和大量的測試資料加以探討改進其處理方法。另外因系統晶片及系統封裝技術的改進，系統級的晶片成本已漸漸降到一般人可接受的範圍，系統封裝的測試需求也逐漸增加，我們在此也提出一些相對應的低成本方案研究。

在第一章裡，我們把近期所遇到的問題及相關的研究結果加以整理，簡略說明過去的一些測試方法。在第一章最後，我們概要的整理說明整篇論文的結構。於第二章和第三章中，我們描述以解碼器為基礎的方案和相對應的方法論，是以選擇性的測試資料壓縮法為基礎。這些方案在送測試資料進晶片測試時能夠避免大量的位元瞬間由0 變1 或由1 變0，進而導致晶片消耗大量功率(switching power)，透過計算的方法，我們可以盡量減少掃瞄鏈(scan chain)上的訊號變動 以達到低功率測試的目的。在第四章中，我們討論泛型(general)的多維度測試方案以達到減低測試功率、測試資料量和測試時間的目的，此方案僅會多出少量的晶片面積。另一方面，隨著技術的進步，系統封裝技術已經普遍，在第五章中我們進一步的探討系統封裝技術，並且提出測試方案在系統封裝中連線測試上的應用。最後在第六章我們總結本論文的貢獻及未來的一些挑戰。

In modern SoC designs, the test strategy is becoming one of the most important issues due to the increase of the test cost, among which we focus on the large test power dissipation and large test data volume. In this dissertation, we propose related test schemes to suppress the test power, test data volume, and test time for test cost reduction. In addition, due to the advancement of SoC/SiP technology, these kinds of technologies become more and more popular today. We also provide some of the low cost SiP test solutions in this dissertation.

We explain the basic idea of the chip test and related works in Chapter 1. In Chapter 2 and 3, we describe the decoder based schemes and methodologies which are based on the selective test pattern compression. These schemes can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. Compared with the previous works, our test scheme achieves relatively small test power and test data volume. In Chapter 4, we propose an adaptive multi-dimensional scan-control scheme which can achieve low test power, small test data volume, and short test time with small area overhead. With the extra scan-control chains, we can access each sub-scan-chain easily and efficiently. Because the scan-control chains are very simple, the area overhead is very small. On the other hand, since System-in-Package (SiP) technique becomes a feasible solution to integrate multiple chips, in Chapter 5, we propose the test schemes which can test the RAM interconnections in SiP efficiently. Our test scheme can generate one test pattern at one cycle. Compared with the boundary scan based test scheme, our test scheme is very fast. Finally, we conclude this dissertation and list some future works in Chapter 6.