系統晶片掃瞄測試之低功耗測試研究

Abstract

SoC 之規模與複雜度日益增大造成掃描式測試上因測試資料量增加使 得測試時間與測試成本提高與測試功率增高。本計畫即擬對上述問題提出 一個解決方案： 我們擬提出一個新的隨機讀取多掃瞄鋉設計架構。與平常之隨機讀取掃瞄 架構不同處為此架構之存取以“行”為讀取單元，而每一行之掃瞄暫存器個 數正是多掃瞄器之個數。它利用一時脈産生器産生時脈來控制所讀取之行掃 瞄鋉而使其他行掃瞄鋉維持不動，如此可達到減省測試圖樣輸入與輸出之功 耗與由時脈産生之功耗。並且我們改進了掃瞄暫存器使之可儲存二個位元之 信號，以至其可不必管掃瞄儲存器之資料相關性而進一步減少圖樣輸出時之 功耗。又此種改進掃瞄暫存器可儲存二個位元之信號，故可應用於二圖樣 (2-pattern)之延遲障礙測試圖樣之壓縮與減低功耗。 我們相信本計畫是第一個提出研究二圖樣延遲障礙測試壓縮之研究者。

Advances on System on Chip in its size and complexity in recent years lead to two issues on scan testing, first, the large size of test data makes test time, consequently, test cost increase; second, the test power also becomes intolerable. In this project, we try to study and offer a solution to above issues. We try to propose a new random access multiple scan design which differs from the conventional random access scan design in its access is addressed by column instead of a single bit. The number of cells of each column is arranged to be the number of scan chains. It utilizes a clock generator to produce clock signals which activate columns during pattern shifting and uses a new scan cell, which can hold two bits, to provide a bypasses path to reduce the transition power of scan path as well as the clock power. It can not only reduce shifting power but also reduce capture power with no need to consider the capture dependency of scan cells. It also can be used for delay test with arbitrary two test patterns to obtain power reduction. We believe that this proposal is the first one which addresses to study scan data compression and test power reduction for 2-pattern delay test.