标题: 系统晶片扫瞄测试之低功耗测试研究
Study on Low Power Scan Testing for SoC
作者: 李崇仁
LEE CHUNG-LEN
国立交通大学电子工程学系及电子研究所
关键字: 系统晶片;扫描测试;测试压缩;测试功耗;System on Chip;Scan Test;Test Compression;Test Power
公开日期: 2008
摘要: SoC 之规模与复杂度日益增大造成扫描式测试上因测试资料量增加使
得测试时间与测试成本提高与测试功率增高。本计画即拟对上述问题提出
一个解决方案:
我们拟提出一个新的随机读取多扫瞄鋉设计架构。与平常之随机读取扫瞄
架构不同处为此架构之存取以“行”为读取单元,而每一行之扫瞄暂存器个
数正是多扫瞄器之个数。它利用一时脉产生器产生时脉来控制所读取之行扫
瞄鋉而使其他行扫瞄鋉维持不动,如此可达到减省测试图样输入与输出之功
耗与由时脉产生之功耗。并且我们改进了扫瞄暂存器使之可储存二个位元之
信号,以至其可不必管扫瞄储存器之资料相关性而进一步减少图样输出时之
功耗。又此种改进扫瞄暂存器可储存二个位元之信号,故可应用于二图样
(2-pattern)之延迟障碍测试图样之压缩与减低功耗。
我们相信本计画是第一个提出研究二图样延迟障碍测试压缩之研究者。
Advances on System on Chip in its size and complexity in recent years lead to two
issues on scan testing, first, the large size of test data makes test time, consequently, test
cost increase; second, the test power also becomes intolerable. In this project, we try to
study and offer a solution to above issues.
We try to propose a new random access multiple scan design which differs from the
conventional random access scan design in its access is addressed by column instead of a
single bit. The number of cells of each column is arranged to be the number of scan chains.
It utilizes a clock generator to produce clock signals which activate columns during pattern
shifting and uses a new scan cell, which can hold two bits, to provide a bypasses path to
reduce the transition power of scan path as well as the clock power. It can not only reduce
shifting power but also reduce capture power with no need to consider the capture
dependency of scan cells. It also can be used for delay test with arbitrary two test patterns
to obtain power reduction.
We believe that this proposal is the first one which addresses to study scan data
compression and test power reduction for 2-pattern delay test.
官方说明文件#: NSC97-2221-E009-177
URI: http://hdl.handle.net/11536/102508
https://www.grb.gov.tw/search/planDetail?id=1686914&docId=290825
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