數位序向電路之振盪環測試

Abstract

在此篇論文中，我們提出一種新的測試方法，即使用振盪環測試原理，來偵測數位序向電路上之定值障礙，並且額外可以偵測一些延遲障礙。我們提出兩種方式來產生測試圖樣：第一種方式，自電路上建構振盪環，來產生測試圖樣，此方式尋找振盪環，將取決於電路之特性；第二種方式，經由狀態轉換表觀察輸出端振盪信號，使用我們所提出之狀態轉換演算法，來產生測試圖樣。另一方面，針對找不到或難以找到測試圖樣之障礙，我們亦提出振盪環方式之序向電路合成之方法，重新設定狀態值，即能找到較為有效之測試圖樣偵測障礙；如此讓這個狀態轉換表，合成後的電路使得可測性提高。實驗結果兩種方式產生之測試圖樣都具有很好之效率。

In this thesis, we propose a novel method for testing using theory of oscillation ring testing. The oscillation ring detects stuck-at fault of the sequential circuit, in addition, it detects the delay fault. We propose two methods for generating the test patterns. The first one method is to create oscillation ring test in the circuit for generating test patterns. The second method is using the state transition table to observe the output of the oscillation ring. For the second method an algorithm has been designed to generate efficient test patterns. Beside, we also alleviate the difficult of test patterns generation by proposing an oscillation ring driven sequential circuit synthesize method which reassigns the state variables to provide an efficient approach for oscillation ring based test pattern generations. Consequently, the testability is great enhanced after the transform of state table. These two methods have been simulated, and got excellent results.