簡化序向電路測試之研究

Abstract

本論文旨在開發新技術來簡化數位系統中序向電路的測試。針對簡化序向 電路產生測試式樣的工作，吾人提出一種簡單且不具太多額外負擔的可測 試性設計法。此法是在序向電路的狀態信號線上跨上一個同位檢查器以用 來提早偵測障礙，此法已經和一個有限狀態機器線路合成系統結合，採用 此法合成的線路其測試式樣的產生變得極為簡單且有效率。為了更進一步 節省硬體負擔，採用部份同位檢查的方式可以在最小的硬體負擔下增加序 向電路的可測試性。針對簡化實際測試時測試式樣的產生，吾人提出一可 用於無掃瞄序向電路的內建式測試式樣產生電路。此測試式樣產生電路是 由一個多序列產生器所構成，該多序列產生器可以產生一序列已具有固定 順序的式樣且允許式樣可重複出現，接著產生假隨機的式樣。如此產生的 測試式樣非常適合於序向性障礙的測試。針對多晶片模組或高度包裝的電 路板上所可能包含的各種不同的線路，可規劃的多序列產生器將能夠有效 的用來測試各種不同的障礙模型。 This dissertation is a result of studies on simplifying sequential circuit testing for digital systems. A simple yet low overhead design for testability scheme is proposed to simplify the sequential test generation. A built-in test vector generator is proposed to simplify the test application for non- scanned sequential circuits. The former scheme employs a parity checker mounting on the state lines of sequential circuits to early detect faults. This scheme had been incorporated into a finite state machine synthesis system. Test generation of such parity checked sequential circuits becomes very simple and effective. To further save the hardware overhead, a partial parity checking scheme is also proposed. Testability of partial parity checked sequential circuits are much enhanced in a very small overhead. The later scheme is constructed by a multiple- sequence generator which can produce a sequence of vectors with a pre-deterministic order as well as recurrent vectors and followed by pseudo-random vectors. The generated vectors are well applicable for sequential fault testing. A programmable multiple-sequence generator is also proposed to be a built-in test vector generator for testing various kinds of circuits and fault models in a multi-chip module or a highly packaged board.