| Title: | 超大型積體電路測試與可測性設計課程發展---子計畫(I)：總論、組合測試、序向測試、設計通例 "VLSI Testing and Design for Testability" Course Development Fundamentals and Design Methodology, Combinational Circuit Testing ,Sequential Circuit Testing and Design Examples |
| Authors: | 周景揚 JOU JING-YANG 國立交通大學電子工程學系 |
| Keywords: | 超大型積體電路設計;超大型積體電路測試;可測試性設計;VLSI design;VLSI testing;Design for testability |
| Issue Date: | 1995 |
| Gov't Doc #: | NSC84-2514-S009-003 |
| URI: | http://hdl.handle.net/11536/96249 https://www.grb.gov.tw/search/planDetail?id=226400&docId=40714 |
| Appears in Collections: | Research Plans |
