標題: Mixed-Vth (MVT) CMOS circuit design for low power cell libraries
作者: Lin, Jiun-Yi
Wang, Li-Rong
Hu, Chia-Lmi
Jou, Shyh-Jye
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2007
摘要: Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.
URI: http://hdl.handle.net/11536/7745
ISBN: 978-1-4244-1592-2
期刊: 20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
起始頁: 181
結束頁: 184
顯示於類別:會議論文