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Parameter extraction method for semiconductor device

dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08691599zh_TW
dc.contributor.authorGuo Jyh-Chyurnen_US
dc.contributor.authorYeh Kuo-Liangen_US
dc.date.accessioned2014-12-16T06:13:52Z
dc.date.available2014-12-16T06:13:52Z
dc.date.issued2014-04-08en_US
dc.description.abstractA parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capacitance per unit area.zh_TW
dc.identifier.govdocG01R031/26zh_TW
dc.identifier.govdocH01L021/66zh_TW
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/104394
dc.language.isozh_TWen_US
dc.titleParameter extraction method for semiconductor devicezh_TW
dc.typePatentsen_US

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