Modeling of the parasitic resistance effect in poly-Si TFTs with LDD structure

dc.citation.epage	532	en_US
dc.citation.spage	529	en_US
dc.contributor.author	Kao, Shih-Chin	en_US
dc.contributor.author	Zan, Hsiao Wen	en_US
dc.contributor.author	Chen, Shih-Ching	en_US
dc.contributor.department	光電工程學系	zh_TW
dc.contributor.department	Department of Photonics	en_US
dc.date.accessioned	2014-12-08T15:25:30Z
dc.date.available	2014-12-08T15:25:30Z
dc.date.issued	2005	en_US
dc.description.abstract	In this study, the model of poly-Si TFTs with LDD structure had been proposed. Firstly, parasitic resistance parameters were extracted from devices with various channel length and LDD length. Then, an accurate I-V model was constructed by combining basic TFT model (RPI model) and the parasitic resistance effects. The model had been verified for devices with channel length larger than 6 mu m. The transconductance behavior in both linear region and saturation region are also well explained by our proposed model.	en_US
dc.identifier.isbn	978-957-28522-2-4	en_US
dc.identifier.journal	IDMC 05: PROCEEDINGS OF THE INTERNATIONAL DISPLAY MANUFACTURING CONFERENCE 2005	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/17908
dc.identifier.wosnumber	WOS:000259399200146
dc.language.iso	en_US	en_US
dc.title	Modeling of the parasitic resistance effect in poly-Si TFTs with LDD structure	en_US
dc.type	Proceedings Paper	en_US

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