A novel fully self-aligned process for high cell density trench gate power MOSFETs

dc.citation.epage	208	en_US
dc.citation.spage	205	en_US
dc.contributor.author	Tsui, BY	en_US
dc.contributor.author	Gan, TC	en_US
dc.contributor.author	Wu, MD	en_US
dc.contributor.author	Chou, HH	en_US
dc.contributor.author	Wu, ZL	en_US
dc.contributor.author	Sune, CT	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:25:51Z
dc.date.available	2014-12-08T15:25:51Z
dc.date.issued	2004	en_US
dc.description.abstract	A novel self-aligned process for high cell density trench gate power MOSFETs with only four mask layers was proposed. The specific on-resistance can be as low as 0.21 mOmega-cm(2) with 1.5um cell pitch and 35V breakdown voltage. Because this process shrinks trench space but not trench width, the quasi-saturation phenomenon is lighter. After optimization the thickness of n- drift layer and n+ substrate, specific on-resistance lower than 0.1 mOmega-cm(2) with 0.6um technology could be expected.	en_US
dc.identifier.isbn	4-88686-060-5	en_US
dc.identifier.journal	ISPSD '04: PROCEEDINGS OF THE 16TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18281
dc.identifier.wosnumber	WOS:000223808200044
dc.language.iso	en_US	en_US
dc.title	A novel fully self-aligned process for high cell density trench gate power MOSFETs	en_US
dc.type	Proceedings Paper	en_US

Files

Now showing 1 - 1 of 1