Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs
| dc.contributor.author | Lee, Ho-Pei | en_US |
| dc.contributor.author | Yu, Chien-Lin | en_US |
| dc.contributor.author | You, Wei-Xiang | en_US |
| dc.contributor.author | Su, Pin | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2018-08-21T05:56:52Z | |
| dc.date.available | 2018-08-21T05:56:52Z | |
| dc.date.issued | 2017-01-01 | en_US |
| dc.identifier.issn | 1930-8868 | en_US |
| dc.identifier.journal | 2017 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/146759 | |
| dc.identifier.wosnumber | WOS:000408991800027 | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs | en_US |
| dc.type | Proceedings Paper | en_US |
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