A 0.4V 53dB SNDR 250 MS/s Time-Based CT Delta Sigma Analog to Digital Converter

Abstract

This paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time Delta Sigma analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 mu W. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm(2).