DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOS
| dc.citation.epage | 1810 | en_US |
| dc.citation.issue | 10 | en_US |
| dc.citation.spage | 1806 | en_US |
| dc.citation.volume | 41 | en_US |
| dc.citation.woscount | 6 | |
| dc.contributor.author | HUANG, CY | en_US |
| dc.contributor.author | CHEN, MJ | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:03:45Z | |
| dc.date.available | 2014-12-08T15:03:45Z | |
| dc.date.issued | 1994-10-01 | en_US |
| dc.description.abstract | This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guideline has been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from guard ring. | en_US |
| dc.identifier.doi | 10.1109/16.324585 | en_US |
| dc.identifier.issn | 0018-9383 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/16.324585 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/2300 | |
| dc.identifier.wosnumber | WOS:A1994PK41000017 | |
| dc.language.iso | en_US | en_US |
| dc.title | DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOS | en_US |
| dc.type | Article | en_US |