New transient detection circuit for system-level ESD protection
| dc.citation.epage | 183 | en_US |
| dc.citation.spage | 180 | en_US |
| dc.contributor.author | Yen, Cheng-Cheng | en_US |
| dc.contributor.author | Liao, Chi-Sheng | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.department | 電機學院 | zh_TW |
| dc.contributor.department | College of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:04:50Z | |
| dc.date.available | 2014-12-08T15:04:50Z | |
| dc.date.issued | 2008 | en_US |
| dc.description.abstract | A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-mu m CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. | en_US |
| dc.identifier.doi | 10.1109/VDAT.2008.4542442 | en_US |
| dc.identifier.isbn | 978-1-4244-1616-5 | en_US |
| dc.identifier.journal | 2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/VDAT.2008.4542442 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/3340 | |
| dc.identifier.wosnumber | WOS:000256565800044 | |
| dc.language.iso | en_US | en_US |
| dc.title | New transient detection circuit for system-level ESD protection | en_US |
| dc.type | Proceedings Paper | en_US |