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Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls

dc.citation.epage31en_US
dc.citation.issue1en_US
dc.citation.spage24en_US
dc.citation.volume4en_US
dc.contributor.authorLo, WYen_US
dc.contributor.authorKer, MDen_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.date.accessioned2014-12-08T15:39:34Z
dc.date.available2014-12-08T15:39:34Z
dc.date.issued2004-03-01en_US
dc.description.abstractAn abnormal failure mechanism due to ESD pulse applied on the nonconnected (NC) solder balls of a high-pin-count (683 balls) BGA packaged chipset IC is presented. The ESD test results of the IC product were found below human-body-model (HBM) 2 kV when stressing all balls or only stressing NC balls, but above HBM 3 kV when stressing all balls excluding NC balls. Failure analyses, including scanning electron microscopy (SEM) photographs and the measurement of current waveforms during ESD discharging event, have been performed. With a new proposed equivalent model, a clear explanation on this unusual phenomenon is found to have a high correlation to the small capacitor method (SCM). Several solutions to overcome this failure mechanism are also discussed.en_US
dc.identifier.doi10.1109/TDMR.2004.824362en_US
dc.identifier.issn1530-4388en_US
dc.identifier.journalIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITYen_US
dc.identifier.urihttp://dx.doi.org/10.1109/TDMR.2004.824362en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/27010
dc.identifier.wosnumberWOS:000220708500005
dc.language.isoen_USen_US
dc.subjectball grid array (BGA)en_US
dc.subjectcharged-device model (CDM)en_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectscanning electron microscopy (SEM)en_US
dc.subjectsmall capacitor method (SCM)en_US
dc.titleAbnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected ballsen_US
dc.typeArticle; Proceedings Paperen_US

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