DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20120044779 | zh_TW |
| dc.contributor.author | Chuang Ching-Te | en_US |
| dc.contributor.author | Yang Hao-I | en_US |
| dc.contributor.author | Lin Yi-Wei | en_US |
| dc.contributor.author | Hwang Wei | en_US |
| dc.contributor.author | Shih Wei-Chiang | en_US |
| dc.contributor.author | Chen Chia-Cheng | en_US |
| dc.date.accessioned | 2014-12-16T06:15:17Z | |
| dc.date.available | 2014-12-16T06:15:17Z | |
| dc.date.issued | 2012-02-23 | en_US |
| dc.description.abstract | A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation. | zh_TW |
| dc.identifier.govdoc | G11C005/14 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/105212 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY | zh_TW |
| dc.type | Patents | en_US |