Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Fan, Ming-Long | en_US |
| dc.contributor.author | Hu, Vita Pi-Ho | en_US |
| dc.contributor.author | Chen, Yin-Nien | en_US |
| dc.contributor.author | Su, Pin | en_US |
| dc.contributor.author | Chuang, Ching-Te | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2015-12-02T03:00:54Z | |
| dc.date.available | 2015-12-02T03:00:54Z | |
| dc.date.issued | 2014-01-01 | en_US |
| dc.description.abstract | In this work, we investigate the impact of interlayer coupling on monolithic 3D 6T/8T SRAM cells with various layouts and tier combinations. Our results indicate that for 3D 6T SRAM cell with NFET in top layer, aligning upper-tier pull-down NFET with bottom-tier pull-up PFET enables better cell stability. For monolithic 3D 8T cell, an area-efficient 4N4P design is evaluated with optimized two-tier layout to enhance cell performance. We find that stacking NFET layer over the PFET tier results in larger design margins for SRAM cell stability and performance. | en_US |
| dc.identifier.isbn | 978-1-4799-2217-8 | en_US |
| dc.identifier.issn | en_US | |
| dc.identifier.journal | PROCEEDINGS OF TECHNICAL PROGRAM - 2014 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/128529 | |
| dc.identifier.wosnumber | WOS:000358865800041 | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling | en_US |
| dc.type | Proceedings Paper | en_US |
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