A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard

dc.citation.epage	224	en_US
dc.citation.spage	219	en_US
dc.contributor.author	Hung, Jui-Hui	en_US
dc.contributor.author	Chen, Sau-Gee	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:15:20Z
dc.date.available	2014-12-08T15:15:20Z
dc.date.issued	2007	en_US
dc.description.abstract	In this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.18 mu m process technology.	en_US
dc.identifier.isbn	978-1-4244-1834-3	en_US
dc.identifier.journal	2007 IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY, VOLS 1-3	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/11512
dc.identifier.wosnumber	WOS:000256344200040
dc.language.iso	en_US	en_US
dc.subject	LDPC code	en_US
dc.subject	decoder	en_US
dc.subject	architecture	en_US
dc.title	A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard	en_US
dc.type	Proceedings Paper	en_US

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