Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation
| dc.citation.epage | 56 | en_US |
| dc.citation.issue | 1 | en_US |
| dc.citation.spage | 48 | en_US |
| dc.citation.volume | 50 | en_US |
| dc.citation.woscount | 1 | |
| dc.contributor.author | Tsai, Hui-Wen | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:07:59Z | |
| dc.date.available | 2014-12-08T15:07:59Z | |
| dc.date.issued | 2010-01-01 | en_US |
| dc.description.abstract | A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-mu m CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCl-X compatible applications. (C) 2009 Elsevier Ltd. All rights reserved. | en_US |
| dc.identifier.doi | 10.1016/j.microrel.2009.09.004 | en_US |
| dc.identifier.issn | 0026-2714 | en_US |
| dc.identifier.journal | MICROELECTRONICS RELIABILITY | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1016/j.microrel.2009.09.004 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/6273 | |
| dc.identifier.wosnumber | WOS:000274610400007 | |
| dc.language.iso | en_US | en_US |
| dc.title | Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation | en_US |
| dc.type | Article | en_US |