DEVICE AND CIRCUIT SIMULATION OF ANOMALOUS DX TRAP EFFECTS IN DCFL AND SCFL HEMT INVERTERS

dc.citation.epage1761en_US
dc.citation.issue11en_US
dc.citation.spage1758en_US
dc.citation.volume12en_US
dc.citation.woscount0
dc.contributor.authorWANG, THen_US
dc.contributor.authorWU, SJen_US
dc.contributor.authorHUANG, CMen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:04:18Z
dc.date.available2014-12-08T15:04:18Z
dc.date.issued1993-11-01en_US
dc.description.abstractAn integrated device and circuit analysis has been developed to evaluate the DX trap induced anomalous transient phenomena in DCFL and SCFL AlGaAs/GaAs HEMT inverters. The slow transient effect and the hysteretic characteristics of the input-output voltage transfer function in the inverters are simulated. The result shows that in comparison with the DCFL inverter, the DX trap effects are much improved in the SCFL inverter due to its particular operational principle.en_US
dc.identifier.doi10.1109/43.248087en_US
dc.identifier.issn0278-0070en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/43.248087en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/2809
dc.identifier.wosnumberWOS:A1993ML08900015
dc.language.isoen_USen_US
dc.titleDEVICE AND CIRCUIT SIMULATION OF ANOMALOUS DX TRAP EFFECTS IN DCFL AND SCFL HEMT INVERTERSen_US
dc.typeArticleen_US

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