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A simple method for sub-100 nm pattern generation with I-line double-patterning technique

dc.citation.epage588en_US
dc.citation.issue5en_US
dc.citation.spage584en_US
dc.citation.volume50en_US
dc.contributor.authorTsai, Tzu-Ien_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorJian, Min-Fengen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:12:51Z
dc.date.available2014-12-08T15:12:51Z
dc.date.issued2010-05-01en_US
dc.description.abstractWe have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal-oxide-semiconductor field-effect transistors. Excellent device characteristics were verified. (C) 2010 Elsevier Ltd. All rights reserved.en_US
dc.identifier.doi10.1016/j.microrel.2010.01.019en_US
dc.identifier.issn0026-2714en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.microrel.2010.01.019en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/9899
dc.identifier.wosnumberWOS:000278728700002
dc.language.isoen_USen_US
dc.titleA simple method for sub-100 nm pattern generation with I-line double-patterning techniqueen_US
dc.typeArticle; Proceedings Paperen_US

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