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A 15b 20MS/s CMOS pipelined ADC with digital background calibration

dc.citation.epage455en_US
dc.citation.spage454en_US
dc.citation.volume47en_US
dc.contributor.authorLiu, HCen_US
dc.contributor.authorLee, ZMen_US
dc.contributor.authorWu, JTen_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.date.accessioned2014-12-08T15:25:47Z
dc.date.available2014-12-08T15:25:47Z
dc.date.issued2004en_US
dc.identifier.isbn0-7803-8267-6en_US
dc.identifier.issn0193-6530en_US
dc.identifier.journal2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERSen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/18214
dc.identifier.wosnumberWOS:000221633800189
dc.language.isoen_USen_US
dc.titleA 15b 20MS/s CMOS pipelined ADC with digital background calibrationen_US
dc.typeProceedings Paperen_US

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