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渦輪解碼器之架構

dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumber200629741zh_TW
dc.contributor.author李鎮宜en_US
dc.contributor.author林建青en_US
dc.contributor.author施彥旭en_US
dc.date.accessioned2014-12-16T06:13:28Z
dc.date.available2014-12-16T06:13:28Z
dc.date.issued2006-08-16en_US
dc.description.abstract本發明提出一種渦輪解碼器之架構,利用一最大後置機率解碼器自一共享記憶體讀取先驗資料,且先驗資料會先經過一讀取位址產生器重排位址後,再經過最大後置機率解碼器運算為數非本徵資料,並經過一寫入位址產生器重排位址,再寫入共享記憶體內,且本發明還設置一快取記憶體,藉此降低對外部記憶體的存取,進而降低功率消耗,且本發明可有效降低共享記憶體使用量,並降低電路複雜度,且可降低成本。zh_TW
dc.identifier.govdocH03M013/00zh_TW
dc.identifier.govdocH03M013/00zh_TW
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/104162
dc.language.isozh_TWen_US
dc.title渦輪解碼器之架構zh_TW
dc.typePatentsen_US

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