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PAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Design

dc.citation.epage1854en_US
dc.citation.spage1849en_US
dc.contributor.authorPan, Po-Chengen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorLin, Chien-Chihen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2018-08-21T05:56:55Z
dc.date.available2018-08-21T05:56:55Z
dc.date.issued2013-01-01en_US
dc.description.abstractThis paper presents an agile hierarchical synthesis framework for analog circuit. To acknowledge the limitation for a given topology analog circuit, this hierarchical synthesis work proposes a performance exploration technique and a non-uniform-step simulation process. Apart from spec targeted designs, this proposed approach can help to search the solutions better than designers' expectation. A parallel genetic algorithm (PAGE) method is employed for performance exploration. Unlike other evolution-based topology explorations, this is the first method that regards performance constraints as input genome for evolution and resolves the multiple-objective problem with the multiple-population feature. Populations of selected performance are transfered to device variables by re-targeting technique. Based on a normalization of device variable distribution, a probabilistic stochastic simulation significantly reduces the convergence time to find the global optima of circuit performance. Experimental results show that our approach on radio-frequency distributed amplifier (RFDA) and folded cascode operational amplifier (Op-Amp) in different technologies can obtain better runtime and higher quality in analog synthesis.en_US
dc.identifier.issn1530-1591en_US
dc.identifier.journalDESIGN, AUTOMATION & TEST IN EUROPEen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/146843
dc.identifier.wosnumberWOS:000415129400354en_US
dc.language.isoen_USen_US
dc.titlePAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Designen_US
dc.typeProceedings Paperen_US

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