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Engineering change order hold time fixing method

dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08839173zh_TW
dc.contributor.authorJiang Hiu-Ruen_US
dc.contributor.authorYang Yu-Mingen_US
dc.contributor.authorHo Sung-Tingen_US
dc.date.accessioned2014-12-16T06:13:48Z
dc.date.available2014-12-16T06:13:48Z
dc.date.issued2014-09-16en_US
dc.description.abstractAn ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output. A load/buffer allocation step is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design.zh_TW
dc.identifier.govdocG06F017/50zh_TW
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/104343
dc.language.isozh_TWen_US
dc.titleEngineering change order hold time fixing methodzh_TW
dc.typePatentsen_US

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